Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 40


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4252d 22h /sdr_ctrl/
39 Test Bench upgradation with bigger data burst size dinesha 4252d 22h /sdr_ctrl/
38 Port Name clean up dinesha 4254d 03h /sdr_ctrl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4254d 05h /sdr_ctrl/
36 Clean up dinesha 4254d 20h /sdr_ctrl/
35 Updated the New Documents - ver 0.1 dinesha 4254d 22h /sdr_ctrl/
34 Removed the older version dinesha 4254d 22h /sdr_ctrl/
33 clean up dinesha 4254d 22h /sdr_ctrl/
32 Debug is enable through +define dinesha 4256d 21h /sdr_ctrl/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4256d 21h /sdr_ctrl/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4256d 21h /sdr_ctrl/
29 SDRAM top and core related run file list are added into svn dinesha 4256d 21h /sdr_ctrl/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4256d 21h /sdr_ctrl/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4257d 19h /sdr_ctrl/
26 invalid log files are removed dinesha 4257d 19h /sdr_ctrl/
25 is renamed as tb_top dinesha 4257d 20h /sdr_ctrl/
24 Clean Up dinesha 4257d 20h /sdr_ctrl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4259d 01h /sdr_ctrl/
22 Pad sdram clock added dinesha 4259d 01h /sdr_ctrl/
21 Clean up dinesha 4259d 01h /sdr_ctrl/
20 8 Bit SDARM support is added dinesha 4260d 20h /sdr_ctrl/
19 8 Bit SDRAM Support added dinesha 4260d 20h /sdr_ctrl/
18 8 Bit SDRAM Support is added dinesha 4260d 20h /sdr_ctrl/
17 micron 8 bit memory models are added into svn dinesha 4260d 20h /sdr_ctrl/
16 8 Bit SDRAM Support is added dinesha 4260d 20h /sdr_ctrl/
15 Port cleanup dinesha 4263d 21h /sdr_ctrl/
14 Unnecessary device config are removed dinesha 4263d 21h /sdr_ctrl/
13 column bit are made progrmmable dinesha 4263d 21h /sdr_ctrl/
12 Column Bits are made programmable dinesha 4263d 21h /sdr_ctrl/
11 SDRAM Specification document added into SVN dinesha 4266d 22h /sdr_ctrl/

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.