URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 49

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
49	clean up	dinesha	4454d 14h	/sdr_ctrl/
48	top-level cleanup	dinesha	4454d 14h	/sdr_ctrl/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4454d 14h	/sdr_ctrl/
46	test bench upgrade + rtl cleanup	dinesha	4456d 15h	/sdr_ctrl/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4456d 19h	/sdr_ctrl/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4458d 17h	/sdr_ctrl/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4458d 19h	/sdr_ctrl/
42	Bug fix in read access is fixed	dinesha	4458d 19h	/sdr_ctrl/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4458d 21h	/sdr_ctrl/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4459d 14h	/sdr_ctrl/
39	Test Bench upgradation with bigger data burst size	dinesha	4459d 14h	/sdr_ctrl/
38	Port Name clean up	dinesha	4460d 19h	/sdr_ctrl/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4460d 20h	/sdr_ctrl/
36	Clean up	dinesha	4461d 11h	/sdr_ctrl/
35	Updated the New Documents - ver 0.1	dinesha	4461d 13h	/sdr_ctrl/
34	Removed the older version	dinesha	4461d 13h	/sdr_ctrl/
33	clean up	dinesha	4461d 13h	/sdr_ctrl/
32	Debug is enable through +define	dinesha	4463d 12h	/sdr_ctrl/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4463d 12h	/sdr_ctrl/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4463d 13h	/sdr_ctrl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 49

Filtering Options