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[/] [sdr_ctrl/] - Rev 68


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Rev Log message Author Age Path
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3573d 13h /sdr_ctrl/
67 time scale removed dinesha 3643d 11h /sdr_ctrl/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 3891d 12h /sdr_ctrl/
65 Updated Log file with CAS latency support 4,5 dinesha 3891d 20h /sdr_ctrl/
64 CAS Latency support added for 4,5 dinesha 3891d 20h /sdr_ctrl/
63 FPGA Bench mark results are added dinesha 4010d 19h /sdr_ctrl/
62 Synthesis constraint for simplify dinesha 4010d 19h /sdr_ctrl/
61 RTL file list are added into SVN dinesha 4010d 20h /sdr_ctrl/
60 warning cleanup dinesha 4010d 20h /sdr_ctrl/
59 Control path request and data are register now for better FPGA timing dinesha 4010d 20h /sdr_ctrl/
58 Read Data is register on RD_FAST=0 case dinesha 4010d 20h /sdr_ctrl/
57 Synthesis constraints are added dinesha 4011d 10h /sdr_ctrl/
56 FPGA Synth optimisation dinesha 4011d 11h /sdr_ctrl/
55 FPGA Synthesis timing optimisation dinesha 4011d 12h /sdr_ctrl/
54 FPGA Timing Optimisation dinesha 4014d 09h /sdr_ctrl/
53 Test bench upgradation dinesha 4015d 10h /sdr_ctrl/
52 Documentation update for request control and transfer control block dinesha 4015d 10h /sdr_ctrl/
51 FPGA relating timing optimisation done dinesha 4015d 10h /sdr_ctrl/
50 Bug fix the request length is fixe dinesha 4017d 14h /sdr_ctrl/
49 clean up dinesha 4018d 13h /sdr_ctrl/

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