URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 68

Rev	Log message	Author	Age	Path
48	top-level cleanup	dinesha	4461d 20h	/sdr_ctrl/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4461d 20h	/sdr_ctrl/
46	test bench upgrade + rtl cleanup	dinesha	4463d 20h	/sdr_ctrl/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4464d 01h	/sdr_ctrl/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4465d 23h	/sdr_ctrl/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4466d 01h	/sdr_ctrl/
42	Bug fix in read access is fixed	dinesha	4466d 01h	/sdr_ctrl/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4466d 02h	/sdr_ctrl/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4466d 19h	/sdr_ctrl/
39	Test Bench upgradation with bigger data burst size	dinesha	4466d 19h	/sdr_ctrl/