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[/] [sdr_ctrl/] [trunk/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 311d 16h /sdr_ctrl/trunk/
72 Command Clean up for model-sim mode dinesha 3305d 01h /sdr_ctrl/trunk/
71 Warning cleanup dinesha 3356d 17h /sdr_ctrl/trunk/
70 Warning Cleanup dinesha 3356d 17h /sdr_ctrl/trunk/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 3356d 18h /sdr_ctrl/trunk/
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3356d 18h /sdr_ctrl/trunk/
67 time scale removed dinesha 3426d 16h /sdr_ctrl/trunk/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 3674d 17h /sdr_ctrl/trunk/
65 Updated Log file with CAS latency support 4,5 dinesha 3675d 01h /sdr_ctrl/trunk/
64 CAS Latency support added for 4,5 dinesha 3675d 01h /sdr_ctrl/trunk/
63 FPGA Bench mark results are added dinesha 3794d 00h /sdr_ctrl/trunk/
62 Synthesis constraint for simplify dinesha 3794d 00h /sdr_ctrl/trunk/
61 RTL file list are added into SVN dinesha 3794d 01h /sdr_ctrl/trunk/
60 warning cleanup dinesha 3794d 01h /sdr_ctrl/trunk/
59 Control path request and data are register now for better FPGA timing dinesha 3794d 01h /sdr_ctrl/trunk/
58 Read Data is register on RD_FAST=0 case dinesha 3794d 01h /sdr_ctrl/trunk/
57 Synthesis constraints are added dinesha 3794d 15h /sdr_ctrl/trunk/
56 FPGA Synth optimisation dinesha 3794d 16h /sdr_ctrl/trunk/
55 FPGA Synthesis timing optimisation dinesha 3794d 17h /sdr_ctrl/trunk/
54 FPGA Timing Optimisation dinesha 3797d 14h /sdr_ctrl/trunk/

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