URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 18

Rev	Log message	Author	Age	Path
18	8 Bit SDRAM Support is added	dinesha	4473d 23h	/sdr_ctrl/trunk/
17	micron 8 bit memory models are added into svn	dinesha	4473d 23h	/sdr_ctrl/trunk/
16	8 Bit SDRAM Support is added	dinesha	4473d 23h	/sdr_ctrl/trunk/
15	Port cleanup	dinesha	4477d 00h	/sdr_ctrl/trunk/
14	Unnecessary device config are removed	dinesha	4477d 00h	/sdr_ctrl/trunk/
13	column bit are made progrmmable	dinesha	4477d 00h	/sdr_ctrl/trunk/
12	Column Bits are made programmable	dinesha	4477d 00h	/sdr_ctrl/trunk/
11	SDRAM Specification document added into SVN	dinesha	4480d 01h	/sdr_ctrl/trunk/
10	Waveform files are added into SVN	dinesha	4480d 01h	/sdr_ctrl/trunk/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4481d 01h	/sdr_ctrl/trunk/
8	test bench files are added into SVN	dinesha	4481d 01h	/sdr_ctrl/trunk/
7	SDRAM Memory Models are added into SVN	dinesha	4481d 01h	/sdr_ctrl/trunk/
6	Golden Log files are added into SVN	dinesha	4481d 01h	/sdr_ctrl/trunk/
5	Run files are updated into SVN	dinesha	4481d 01h	/sdr_ctrl/trunk/
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4481d 22h	/sdr_ctrl/trunk/
3	SDRAM controller core files are checked in	dinesha	4488d 08h	/sdr_ctrl/trunk/
2		dinesha	4491d 00h	/sdr_ctrl/trunk/
1	The project and the structure was created	root	4495d 00h	/sdr_ctrl/trunk/