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[/] [sdr_ctrl/] [trunk/] - Rev 27

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Rev Log message Author Age Path
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4551d 04h /sdr_ctrl/trunk/
26 invalid log files are removed dinesha 4551d 04h /sdr_ctrl/trunk/
25 tb.sv is renamed as tb_top dinesha 4551d 04h /sdr_ctrl/trunk/
24 Clean Up dinesha 4551d 04h /sdr_ctrl/trunk/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4552d 10h /sdr_ctrl/trunk/
22 Pad sdram clock added dinesha 4552d 10h /sdr_ctrl/trunk/
21 Clean up dinesha 4552d 10h /sdr_ctrl/trunk/
20 8 Bit SDARM support is added dinesha 4554d 04h /sdr_ctrl/trunk/
19 8 Bit SDRAM Support added dinesha 4554d 04h /sdr_ctrl/trunk/
18 8 Bit SDRAM Support is added dinesha 4554d 05h /sdr_ctrl/trunk/
17 micron 8 bit memory models are added into svn dinesha 4554d 05h /sdr_ctrl/trunk/
16 8 Bit SDRAM Support is added dinesha 4554d 05h /sdr_ctrl/trunk/
15 Port cleanup dinesha 4557d 05h /sdr_ctrl/trunk/
14 Unnecessary device config are removed dinesha 4557d 05h /sdr_ctrl/trunk/
13 column bit are made progrmmable dinesha 4557d 06h /sdr_ctrl/trunk/
12 Column Bits are made programmable dinesha 4557d 06h /sdr_ctrl/trunk/
11 SDRAM Specification document added into SVN dinesha 4560d 07h /sdr_ctrl/trunk/
10 Waveform files are added into SVN dinesha 4560d 07h /sdr_ctrl/trunk/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4561d 06h /sdr_ctrl/trunk/
8 test bench files are added into SVN dinesha 4561d 06h /sdr_ctrl/trunk/
7 SDRAM Memory Models are added into SVN dinesha 4561d 06h /sdr_ctrl/trunk/
6 Golden Log files are added into SVN dinesha 4561d 07h /sdr_ctrl/trunk/
5 Run files are updated into SVN dinesha 4561d 07h /sdr_ctrl/trunk/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4562d 04h /sdr_ctrl/trunk/
3 SDRAM controller core files are checked in dinesha 4568d 14h /sdr_ctrl/trunk/
2 dinesha 4571d 06h /sdr_ctrl/trunk/
1 The project and the structure was created root 4575d 06h /sdr_ctrl/trunk/

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