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Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 971d 12h /sdr_ctrl/trunk/
72 Command Clean up for model-sim mode dinesha 3964d 20h /sdr_ctrl/trunk/
71 Warning cleanup dinesha 4016d 13h /sdr_ctrl/trunk/
70 Warning Cleanup dinesha 4016d 13h /sdr_ctrl/trunk/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4016d 14h /sdr_ctrl/trunk/
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4016d 14h /sdr_ctrl/trunk/
67 time scale removed dinesha 4086d 12h /sdr_ctrl/trunk/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4334d 13h /sdr_ctrl/trunk/
65 Updated Log file with CAS latency support 4,5 dinesha 4334d 21h /sdr_ctrl/trunk/
64 CAS Latency support added for 4,5 dinesha 4334d 21h /sdr_ctrl/trunk/
63 FPGA Bench mark results are added dinesha 4453d 20h /sdr_ctrl/trunk/
62 Synthesis constraint for simplify dinesha 4453d 20h /sdr_ctrl/trunk/
61 RTL file list are added into SVN dinesha 4453d 21h /sdr_ctrl/trunk/
60 warning cleanup dinesha 4453d 21h /sdr_ctrl/trunk/
59 Control path request and data are register now for better FPGA timing dinesha 4453d 21h /sdr_ctrl/trunk/
58 Read Data is register on RD_FAST=0 case dinesha 4453d 21h /sdr_ctrl/trunk/
57 Synthesis constraints are added dinesha 4454d 11h /sdr_ctrl/trunk/
56 FPGA Synth optimisation dinesha 4454d 12h /sdr_ctrl/trunk/
55 FPGA Synthesis timing optimisation dinesha 4454d 13h /sdr_ctrl/trunk/
54 FPGA Timing Optimisation dinesha 4457d 10h /sdr_ctrl/trunk/
53 Test bench upgradation dinesha 4458d 11h /sdr_ctrl/trunk/
52 Documentation update for request control and transfer control block dinesha 4458d 11h /sdr_ctrl/trunk/
51 FPGA relating timing optimisation done dinesha 4458d 11h /sdr_ctrl/trunk/
50 Bug fix the request length is fixe dinesha 4460d 15h /sdr_ctrl/trunk/
49 clean up dinesha 4461d 14h /sdr_ctrl/trunk/
48 top-level cleanup dinesha 4461d 14h /sdr_ctrl/trunk/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4461d 14h /sdr_ctrl/trunk/
46 test bench upgrade + rtl cleanup dinesha 4463d 15h /sdr_ctrl/trunk/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4463d 19h /sdr_ctrl/trunk/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4465d 17h /sdr_ctrl/trunk/

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