URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 73

Rev	Log message	Author	Age	Path
38	Port Name clean up	dinesha	4461d 07h	/sdr_ctrl/trunk/rtl/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4461d 09h	/sdr_ctrl/trunk/rtl/
36	Clean up	dinesha	4462d 00h	/sdr_ctrl/trunk/rtl/
33	clean up	dinesha	4462d 02h	/sdr_ctrl/trunk/rtl/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4464d 01h	/sdr_ctrl/trunk/rtl/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4466d 05h	/sdr_ctrl/trunk/rtl/
16	8 Bit SDRAM Support is added	dinesha	4468d 00h	/sdr_ctrl/trunk/rtl/
15	Port cleanup	dinesha	4471d 01h	/sdr_ctrl/trunk/rtl/
13	column bit are made progrmmable	dinesha	4471d 01h	/sdr_ctrl/trunk/rtl/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4475d 02h	/sdr_ctrl/trunk/rtl/