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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] - Rev 42

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Rev Log message Author Age Path
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4558d 03h /sdr_ctrl/trunk/rtl/core/
36 Clean up dinesha 4558d 18h /sdr_ctrl/trunk/rtl/core/
33 clean up dinesha 4558d 20h /sdr_ctrl/trunk/rtl/core/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4560d 19h /sdr_ctrl/trunk/rtl/core/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4562d 23h /sdr_ctrl/trunk/rtl/core/
16 8 Bit SDRAM Support is added dinesha 4564d 18h /sdr_ctrl/trunk/rtl/core/
15 Port cleanup dinesha 4567d 19h /sdr_ctrl/trunk/rtl/core/
13 column bit are made progrmmable dinesha 4567d 19h /sdr_ctrl/trunk/rtl/core/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4571d 20h /sdr_ctrl/trunk/rtl/core/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4572d 17h /sdr_ctrl/trunk/rtl/core/
3 SDRAM controller core files are checked in dinesha 4579d 04h /sdr_ctrl/trunk/rtl/core/

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