OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] - Rev 42

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4440d 12h /sdr_ctrl/trunk/rtl/core/
36 Clean up dinesha 4441d 03h /sdr_ctrl/trunk/rtl/core/
33 clean up dinesha 4441d 05h /sdr_ctrl/trunk/rtl/core/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4443d 04h /sdr_ctrl/trunk/rtl/core/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4445d 08h /sdr_ctrl/trunk/rtl/core/
16 8 Bit SDRAM Support is added dinesha 4447d 03h /sdr_ctrl/trunk/rtl/core/
15 Port cleanup dinesha 4450d 04h /sdr_ctrl/trunk/rtl/core/
13 column bit are made progrmmable dinesha 4450d 04h /sdr_ctrl/trunk/rtl/core/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4454d 05h /sdr_ctrl/trunk/rtl/core/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4455d 02h /sdr_ctrl/trunk/rtl/core/
3 SDRAM controller core files are checked in dinesha 4461d 12h /sdr_ctrl/trunk/rtl/core/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.