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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] - Rev 60

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Rev Log message Author Age Path
55 FPGA Synthesis timing optimisation dinesha 5017d 18h /sdr_ctrl/trunk/rtl/core/
54 FPGA Timing Optimisation dinesha 5020d 16h /sdr_ctrl/trunk/rtl/core/
51 FPGA relating timing optimisation done dinesha 5021d 17h /sdr_ctrl/trunk/rtl/core/
50 Bug fix the request length is fixe dinesha 5023d 20h /sdr_ctrl/trunk/rtl/core/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 5024d 19h /sdr_ctrl/trunk/rtl/core/
46 test bench upgrade + rtl cleanup dinesha 5026d 20h /sdr_ctrl/trunk/rtl/core/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 5027d 00h /sdr_ctrl/trunk/rtl/core/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 5028d 23h /sdr_ctrl/trunk/rtl/core/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 5031d 02h /sdr_ctrl/trunk/rtl/core/
36 Clean up dinesha 5031d 17h /sdr_ctrl/trunk/rtl/core/
33 clean up dinesha 5031d 19h /sdr_ctrl/trunk/rtl/core/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 5033d 18h /sdr_ctrl/trunk/rtl/core/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 5035d 22h /sdr_ctrl/trunk/rtl/core/
16 8 Bit SDRAM Support is added dinesha 5037d 17h /sdr_ctrl/trunk/rtl/core/
15 Port cleanup dinesha 5040d 17h /sdr_ctrl/trunk/rtl/core/
13 column bit are made progrmmable dinesha 5040d 18h /sdr_ctrl/trunk/rtl/core/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 5044d 19h /sdr_ctrl/trunk/rtl/core/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 5045d 16h /sdr_ctrl/trunk/rtl/core/
3 SDRAM controller core files are checked in dinesha 5052d 02h /sdr_ctrl/trunk/rtl/core/

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