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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 36

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Rev Log message Author Age Path
33 clean up dinesha 4701d 06h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4703d 05h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4705d 09h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
16 8 Bit SDRAM Support is added dinesha 4707d 04h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
15 Port cleanup dinesha 4710d 04h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
13 column bit are made progrmmable dinesha 4710d 05h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4714d 05h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4715d 03h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
3 SDRAM controller core files are checked in dinesha 4721d 13h /sdr_ctrl/trunk/rtl/core/sdrc_core.v

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