URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_define.v] - Rev 60

Rev	Log message	Author	Age	Path
54	FPGA Timing Optimisation	dinesha	5052d 08h	/sdr_ctrl/trunk/rtl/core/sdrc_define.v
51	FPGA relating timing optimisation done	dinesha	5053d 09h	/sdr_ctrl/trunk/rtl/core/sdrc_define.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	5062d 18h	/sdr_ctrl/trunk/rtl/core/sdrc_define.v
15	Port cleanup	dinesha	5072d 10h	/sdr_ctrl/trunk/rtl/core/sdrc.def
13	column bit are made progrmmable	dinesha	5072d 10h	/sdr_ctrl/trunk/rtl/core/sdrc.def
3	SDRAM controller core files are checked in	dinesha	5083d 18h	/sdr_ctrl/trunk/rtl/core/sdrc.def