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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_define.v] - Rev 73


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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 351d 04h /sdr_ctrl/trunk/rtl/core/sdrc_define.v
54 FPGA Timing Optimisation dinesha 3837d 02h /sdr_ctrl/trunk/rtl/core/sdrc_define.v
51 FPGA relating timing optimisation done dinesha 3838d 03h /sdr_ctrl/trunk/rtl/core/sdrc_define.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 3847d 12h /sdr_ctrl/trunk/rtl/core/sdrc_define.v
15 Port cleanup dinesha 3857d 04h /sdr_ctrl/trunk/rtl/core/sdrc.def
13 column bit are made progrmmable dinesha 3857d 04h /sdr_ctrl/trunk/rtl/core/sdrc.def
3 SDRAM controller core files are checked in dinesha 3868d 13h /sdr_ctrl/trunk/rtl/core/sdrc.def

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