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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_req_gen.v] - Rev 37

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Rev Log message Author Age Path
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4441d 01h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
33 clean up dinesha 4441d 18h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
16 8 Bit SDRAM Support is added dinesha 4447d 16h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
15 Port cleanup dinesha 4450d 17h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
13 column bit are made progrmmable dinesha 4450d 17h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
3 SDRAM controller core files are checked in dinesha 4462d 01h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v

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