URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_req_gen.v] - Rev 60

Rev	Log message	Author	Age	Path
55	FPGA Synthesis timing optimisation	dinesha	5053d 16h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
54	FPGA Timing Optimisation	dinesha	5056d 13h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
51	FPGA relating timing optimisation done	dinesha	5057d 14h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
50	Bug fix the request length is fixe	dinesha	5059d 18h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	5060d 17h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
46	test bench upgrade + rtl cleanup	dinesha	5062d 18h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	5062d 22h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	5066d 23h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
33	clean up	dinesha	5067d 16h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
16	8 Bit SDRAM Support is added	dinesha	5073d 14h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
15	Port cleanup	dinesha	5076d 15h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
13	column bit are made progrmmable	dinesha	5076d 15h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
3	SDRAM controller core files are checked in	dinesha	5088d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v