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[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc/] - Rev 69


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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 3687d 21h /sdr_ctrl/trunk/rtl/wb2sdrc/
59 Control path request and data are register now for better FPGA timing dinesha 4125d 04h /sdr_ctrl/trunk/rtl/wb2sdrc/
55 FPGA Synthesis timing optimisation dinesha 4125d 20h /sdr_ctrl/trunk/rtl/wb2sdrc/
42 Bug fix in read access is fixed dinesha 4137d 02h /sdr_ctrl/trunk/rtl/wb2sdrc/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4137d 20h /sdr_ctrl/trunk/rtl/wb2sdrc/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4139d 03h /sdr_ctrl/trunk/rtl/wb2sdrc/
33 clean up dinesha 4139d 20h /sdr_ctrl/trunk/rtl/wb2sdrc/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4141d 19h /sdr_ctrl/trunk/rtl/wb2sdrc/

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