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[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc/] - Rev 40

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Rev Log message Author Age Path
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4440d 02h /sdr_ctrl/trunk/rtl/wb2sdrc/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4441d 09h /sdr_ctrl/trunk/rtl/wb2sdrc/
33 clean up dinesha 4442d 02h /sdr_ctrl/trunk/rtl/wb2sdrc/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4444d 01h /sdr_ctrl/trunk/rtl/wb2sdrc/

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