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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

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[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 943d 20h /sdr_ctrl/trunk/verif
72 Command Clean up for model-sim mode dinesha 3937d 04h /sdr_ctrl/trunk/verif
70 Warning Cleanup dinesha 3988d 21h /sdr_ctrl/trunk/verif
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3988d 22h /sdr_ctrl/trunk/verif
65 Updated Log file with CAS latency support 4,5 dinesha 4307d 05h /sdr_ctrl/trunk/verif
56 FPGA Synth optimisation dinesha 4426d 20h /sdr_ctrl/trunk/verif
53 Test bench upgradation dinesha 4430d 18h /sdr_ctrl/trunk/verif
49 clean up dinesha 4433d 22h /sdr_ctrl/trunk/verif
48 top-level cleanup dinesha 4433d 22h /sdr_ctrl/trunk/verif
46 test bench upgrade + rtl cleanup dinesha 4435d 23h /sdr_ctrl/trunk/verif
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4436d 03h /sdr_ctrl/trunk/verif
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4438d 01h /sdr_ctrl/trunk/verif
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4438d 03h /sdr_ctrl/trunk/verif
39 Test Bench upgradation with bigger data burst size dinesha 4438d 22h /sdr_ctrl/trunk/verif
38 Port Name clean up dinesha 4440d 03h /sdr_ctrl/trunk/verif
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4440d 04h /sdr_ctrl/trunk/verif
33 clean up dinesha 4440d 21h /sdr_ctrl/trunk/verif
32 Debug is enable through +define dinesha 4442d 20h /sdr_ctrl/trunk/verif
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4442d 20h /sdr_ctrl/trunk/verif
29 SDRAM top and core related run file list are added into svn dinesha 4442d 20h /sdr_ctrl/trunk/verif

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