URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 22

Rev	Log message	Author	Age	Path
22	Pad sdram clock added	dinesha	4473d 00h	/sdr_ctrl/trunk/verif/
21	Clean up	dinesha	4473d 00h	/sdr_ctrl/trunk/verif/
20	8 Bit SDARM support is added	dinesha	4474d 19h	/sdr_ctrl/trunk/verif/
19	8 Bit SDRAM Support added	dinesha	4474d 19h	/sdr_ctrl/trunk/verif/
18	8 Bit SDRAM Support is added	dinesha	4474d 19h	/sdr_ctrl/trunk/verif/
17	micron 8 bit memory models are added into svn	dinesha	4474d 19h	/sdr_ctrl/trunk/verif/
14	Unnecessary device config are removed	dinesha	4477d 20h	/sdr_ctrl/trunk/verif/
12	Column Bits are made programmable	dinesha	4477d 20h	/sdr_ctrl/trunk/verif/
10	Waveform files are added into SVN	dinesha	4480d 21h	/sdr_ctrl/trunk/verif/
8	test bench files are added into SVN	dinesha	4481d 21h	/sdr_ctrl/trunk/verif/
7	SDRAM Memory Models are added into SVN	dinesha	4481d 21h	/sdr_ctrl/trunk/verif/
6	Golden Log files are added into SVN	dinesha	4481d 21h	/sdr_ctrl/trunk/verif/
5	Run files are updated into SVN	dinesha	4481d 21h	/sdr_ctrl/trunk/verif/
2		dinesha	4491d 20h	/sdr_ctrl/trunk/verif/