OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 39

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
39 Test Bench upgradation with bigger data burst size dinesha 4466d 07h /sdr_ctrl/trunk/verif/
38 Port Name clean up dinesha 4467d 12h /sdr_ctrl/trunk/verif/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4467d 14h /sdr_ctrl/trunk/verif/
33 clean up dinesha 4468d 07h /sdr_ctrl/trunk/verif/
32 Debug is enable through +define dinesha 4470d 06h /sdr_ctrl/trunk/verif/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4470d 06h /sdr_ctrl/trunk/verif/
29 SDRAM top and core related run file list are added into svn dinesha 4470d 06h /sdr_ctrl/trunk/verif/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4470d 06h /sdr_ctrl/trunk/verif/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4471d 04h /sdr_ctrl/trunk/verif/
26 invalid log files are removed dinesha 4471d 04h /sdr_ctrl/trunk/verif/
25 tb.sv is renamed as tb_top dinesha 4471d 05h /sdr_ctrl/trunk/verif/
24 Clean Up dinesha 4471d 05h /sdr_ctrl/trunk/verif/
22 Pad sdram clock added dinesha 4472d 10h /sdr_ctrl/trunk/verif/
21 Clean up dinesha 4472d 10h /sdr_ctrl/trunk/verif/
20 8 Bit SDARM support is added dinesha 4474d 05h /sdr_ctrl/trunk/verif/
19 8 Bit SDRAM Support added dinesha 4474d 05h /sdr_ctrl/trunk/verif/
18 8 Bit SDRAM Support is added dinesha 4474d 05h /sdr_ctrl/trunk/verif/
17 micron 8 bit memory models are added into svn dinesha 4474d 05h /sdr_ctrl/trunk/verif/
14 Unnecessary device config are removed dinesha 4477d 06h /sdr_ctrl/trunk/verif/
12 Column Bits are made programmable dinesha 4477d 06h /sdr_ctrl/trunk/verif/
10 Waveform files are added into SVN dinesha 4480d 07h /sdr_ctrl/trunk/verif/
8 test bench files are added into SVN dinesha 4481d 07h /sdr_ctrl/trunk/verif/
7 SDRAM Memory Models are added into SVN dinesha 4481d 07h /sdr_ctrl/trunk/verif/
6 Golden Log files are added into SVN dinesha 4481d 07h /sdr_ctrl/trunk/verif/
5 Run files are updated into SVN dinesha 4481d 07h /sdr_ctrl/trunk/verif/
2 dinesha 4491d 06h /sdr_ctrl/trunk/verif/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.