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[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 44

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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4438d 01h /sdr_ctrl/trunk/verif
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4438d 03h /sdr_ctrl/trunk/verif
39 Test Bench upgradation with bigger data burst size dinesha 4438d 22h /sdr_ctrl/trunk/verif
38 Port Name clean up dinesha 4440d 03h /sdr_ctrl/trunk/verif
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4440d 05h /sdr_ctrl/trunk/verif
33 clean up dinesha 4440d 22h /sdr_ctrl/trunk/verif
32 Debug is enable through +define dinesha 4442d 20h /sdr_ctrl/trunk/verif
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4442d 21h /sdr_ctrl/trunk/verif
29 SDRAM top and core related run file list are added into svn dinesha 4442d 21h /sdr_ctrl/trunk/verif
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4442d 21h /sdr_ctrl/trunk/verif
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4443d 19h /sdr_ctrl/trunk/verif
26 invalid log files are removed dinesha 4443d 19h /sdr_ctrl/trunk/verif
25 tb.sv is renamed as tb_top dinesha 4443d 19h /sdr_ctrl/trunk/verif
24 Clean Up dinesha 4443d 19h /sdr_ctrl/trunk/verif
22 Pad sdram clock added dinesha 4445d 01h /sdr_ctrl/trunk/verif
21 Clean up dinesha 4445d 01h /sdr_ctrl/trunk/verif
20 8 Bit SDARM support is added dinesha 4446d 19h /sdr_ctrl/trunk/verif
19 8 Bit SDRAM Support added dinesha 4446d 19h /sdr_ctrl/trunk/verif
18 8 Bit SDRAM Support is added dinesha 4446d 19h /sdr_ctrl/trunk/verif
17 micron 8 bit memory models are added into svn dinesha 4446d 19h /sdr_ctrl/trunk/verif

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