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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] - Rev 43

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Rev Log message Author Age Path
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4438d 05h /sdr_ctrl/trunk/verif/log/
39 Test Bench upgradation with bigger data burst size dinesha 4438d 23h /sdr_ctrl/trunk/verif/log/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4440d 06h /sdr_ctrl/trunk/verif/log/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4442d 22h /sdr_ctrl/trunk/verif/log/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4443d 20h /sdr_ctrl/trunk/verif/log/
26 invalid log files are removed dinesha 4443d 21h /sdr_ctrl/trunk/verif/log/
21 Clean up dinesha 4445d 02h /sdr_ctrl/trunk/verif/log/
20 8 Bit SDARM support is added dinesha 4446d 21h /sdr_ctrl/trunk/verif/log/
6 Golden Log files are added into SVN dinesha 4453d 23h /sdr_ctrl/trunk/verif/log/
2 dinesha 4463d 22h /sdr_ctrl/trunk/verif/log/

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