OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] - Rev 56

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
56 FPGA Synth optimisation dinesha 4426d 23h /sdr_ctrl/trunk/verif/log/
53 Test bench upgradation dinesha 4430d 21h /sdr_ctrl/trunk/verif/log/
49 clean up dinesha 4434d 00h /sdr_ctrl/trunk/verif/log/
48 top-level cleanup dinesha 4434d 00h /sdr_ctrl/trunk/verif/log/
46 test bench upgrade + rtl cleanup dinesha 4436d 01h /sdr_ctrl/trunk/verif/log/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4436d 06h /sdr_ctrl/trunk/verif/log/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4438d 04h /sdr_ctrl/trunk/verif/log/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4438d 05h /sdr_ctrl/trunk/verif/log/
39 Test Bench upgradation with bigger data burst size dinesha 4439d 00h /sdr_ctrl/trunk/verif/log/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4440d 07h /sdr_ctrl/trunk/verif/log/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4442d 23h /sdr_ctrl/trunk/verif/log/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4443d 21h /sdr_ctrl/trunk/verif/log/
26 invalid log files are removed dinesha 4443d 21h /sdr_ctrl/trunk/verif/log/
21 Clean up dinesha 4445d 03h /sdr_ctrl/trunk/verif/log/
20 8 Bit SDARM support is added dinesha 4446d 22h /sdr_ctrl/trunk/verif/log/
6 Golden Log files are added into SVN dinesha 4454d 00h /sdr_ctrl/trunk/verif/log/
2 dinesha 4463d 23h /sdr_ctrl/trunk/verif/log/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.