URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_SDR_16BIT_basic_test1.log] - Rev 56

Rev	Log message	Author	Age	Path
56	FPGA Synth optimisation	dinesha	4617d 23h	/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
53	Test bench upgradation	dinesha	4621d 22h	/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
49	clean up	dinesha	4625d 01h	/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
48	top-level cleanup	dinesha	4625d 01h	/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
46	test bench upgrade + rtl cleanup	dinesha	4627d 02h	/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4627d 06h	/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4629d 06h	/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4634d 00h	/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4634d 22h	/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log