Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_SDR_32BIT_basic_test1.log] - Rev 56


Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
56 FPGA Synth optimisation dinesha 4541d 10h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
53 Test bench upgradation dinesha 4545d 08h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
49 clean up dinesha 4548d 11h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
48 top-level cleanup dinesha 4548d 11h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
46 test bench upgrade + rtl cleanup dinesha 4550d 12h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4550d 16h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4552d 16h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4557d 10h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4558d 08h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.