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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_SDR_8BIT_complie.log] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 943d 19h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log
65 Updated Log file with CAS latency support 4,5 dinesha 4307d 04h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4443d 18h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log

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