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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_sdr16_sim.log] - Rev 65

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Rev Log message Author Age Path
65 Updated Log file with CAS latency support 4,5 dinesha 4508d 08h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
56 FPGA Synth optimisation dinesha 4627d 23h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
53 Test bench upgradation dinesha 4631d 21h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
49 clean up dinesha 4635d 01h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
48 top-level cleanup dinesha 4635d 01h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
46 test bench upgrade + rtl cleanup dinesha 4637d 02h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4637d 06h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4639d 06h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4644d 00h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4644d 22h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log

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