URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_sdr16_sim.log] - Rev 65

Rev	Log message	Author	Age	Path
65	Updated Log file with CAS latency support 4,5	dinesha	4122d 05h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
56	FPGA Synth optimisation	dinesha	4241d 21h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
53	Test bench upgradation	dinesha	4245d 19h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
49	clean up	dinesha	4248d 22h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
48	top-level cleanup	dinesha	4248d 22h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
46	test bench upgrade + rtl cleanup	dinesha	4250d 23h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4251d 03h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4253d 03h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4257d 21h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4258d 19h	/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log