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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_sdr16_sim.log] - Rev 48


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Rev Log message Author Age Path
48 top-level cleanup dinesha 4065d 02h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
46 test bench upgrade + rtl cleanup dinesha 4067d 03h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4067d 07h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4069d 07h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4074d 01h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4074d 23h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log

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