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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_sdr16_sim.log] - Rev 48

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Rev Log message Author Age Path
48 top-level cleanup dinesha 4628d 00h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
46 test bench upgrade + rtl cleanup dinesha 4630d 01h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4630d 05h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4632d 05h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4636d 23h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4637d 21h /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log

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