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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_SDR_32BIT_basic_test1.log] - Rev 65


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Rev Log message Author Age Path
65 Updated Log file with CAS latency support 4,5 dinesha 4131d 18h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
56 FPGA Synth optimisation dinesha 4251d 09h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
53 Test bench upgradation dinesha 4255d 07h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
48 top-level cleanup dinesha 4258d 11h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
46 test bench upgrade + rtl cleanup dinesha 4260d 12h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4260d 16h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4262d 16h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
39 Test Bench upgradation with bigger data burst size dinesha 4263d 11h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4264d 17h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4267d 10h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log

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