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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_SDR_32BIT_basic_test1.log] - Rev 56

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Rev Log message Author Age Path
56 FPGA Synth optimisation dinesha 4426d 22h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
53 Test bench upgradation dinesha 4430d 21h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
48 top-level cleanup dinesha 4434d 00h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
46 test bench upgrade + rtl cleanup dinesha 4436d 01h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4436d 05h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4438d 05h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
39 Test Bench upgradation with bigger data burst size dinesha 4439d 00h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4440d 06h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4442d 23h /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log

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