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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr16_sim.log] - Rev 65


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Rev Log message Author Age Path
65 Updated Log file with CAS latency support 4,5 dinesha 4424d 10h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
56 FPGA Synth optimisation dinesha 4544d 02h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
53 Test bench upgradation dinesha 4548d 00h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
48 top-level cleanup dinesha 4551d 03h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
46 test bench upgrade + rtl cleanup dinesha 4553d 04h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4553d 09h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4555d 07h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4555d 08h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
39 Test Bench upgradation with bigger data burst size dinesha 4556d 03h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4557d 10h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4560d 02h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log

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