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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr32_sim.log] - Rev 39

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Rev Log message Author Age Path
39 Test Bench upgradation with bigger data burst size dinesha 4630d 10h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4631d 16h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4634d 09h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log

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