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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr8_sim.log] - Rev 46

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Rev Log message Author Age Path
46 test bench upgrade + rtl cleanup dinesha 4436d 11h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4436d 15h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4438d 13h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4438d 15h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
39 Test Bench upgradation with bigger data burst size dinesha 4439d 10h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4440d 17h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4443d 09h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log

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