OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [run/] - Rev 48

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4608d 07h /sdr_ctrl/trunk/verif/run/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4610d 07h /sdr_ctrl/trunk/verif/run/
33 clean up dinesha 4613d 01h /sdr_ctrl/trunk/verif/run/
29 SDRAM top and core related run file list are added into svn dinesha 4615d 00h /sdr_ctrl/trunk/verif/run/
19 8 Bit SDRAM Support added dinesha 4618d 23h /sdr_ctrl/trunk/verif/run/
5 Run files are updated into SVN dinesha 4626d 01h /sdr_ctrl/trunk/verif/run/
2 dinesha 4636d 00h /sdr_ctrl/trunk/verif/run/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.