URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 30

Rev	Log message	Author	Age	Path
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	3958d 15h	/sdr_ctrl/trunk/verif/tb/
25	tb.sv is renamed as tb_top	dinesha	3959d 14h	/sdr_ctrl/trunk/verif/tb/
24	Clean Up	dinesha	3959d 14h	/sdr_ctrl/trunk/verif/tb/
22	Pad sdram clock added	dinesha	3960d 19h	/sdr_ctrl/trunk/verif/tb/
18	8 Bit SDRAM Support is added	dinesha	3962d 14h	/sdr_ctrl/trunk/verif/tb/
14	Unnecessary device config are removed	dinesha	3965d 15h	/sdr_ctrl/trunk/verif/tb/
12	Column Bits are made programmable	dinesha	3965d 15h	/sdr_ctrl/trunk/verif/tb/
8	test bench files are added into SVN	dinesha	3969d 16h	/sdr_ctrl/trunk/verif/tb/
2		dinesha	3979d 15h	/sdr_ctrl/trunk/verif/tb/