URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 33

Rev	Log message	Author	Age	Path
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4470d 13h	/sdr_ctrl/trunk/verif/tb/
25	tb.sv is renamed as tb_top	dinesha	4471d 12h	/sdr_ctrl/trunk/verif/tb/
24	Clean Up	dinesha	4471d 12h	/sdr_ctrl/trunk/verif/tb/
22	Pad sdram clock added	dinesha	4472d 17h	/sdr_ctrl/trunk/verif/tb/
18	8 Bit SDRAM Support is added	dinesha	4474d 12h	/sdr_ctrl/trunk/verif/tb/
14	Unnecessary device config are removed	dinesha	4477d 13h	/sdr_ctrl/trunk/verif/tb/
12	Column Bits are made programmable	dinesha	4477d 13h	/sdr_ctrl/trunk/verif/tb/
8	test bench files are added into SVN	dinesha	4481d 14h	/sdr_ctrl/trunk/verif/tb/
2		dinesha	4491d 13h	/sdr_ctrl/trunk/verif/tb/