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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 35

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30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4551d 19h /sdr_ctrl/trunk/verif/tb/
25 tb.sv is renamed as tb_top dinesha 4552d 18h /sdr_ctrl/trunk/verif/tb/
24 Clean Up dinesha 4552d 18h /sdr_ctrl/trunk/verif/tb/
22 Pad sdram clock added dinesha 4553d 23h /sdr_ctrl/trunk/verif/tb/
18 8 Bit SDRAM Support is added dinesha 4555d 18h /sdr_ctrl/trunk/verif/tb/
14 Unnecessary device config are removed dinesha 4558d 19h /sdr_ctrl/trunk/verif/tb/
12 Column Bits are made programmable dinesha 4558d 19h /sdr_ctrl/trunk/verif/tb/
8 test bench files are added into SVN dinesha 4562d 20h /sdr_ctrl/trunk/verif/tb/
2 dinesha 4572d 20h /sdr_ctrl/trunk/verif/tb/

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