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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 971d 15h /sdr_ctrl/trunk/verif/tb
70 Warning Cleanup dinesha 4016d 16h /sdr_ctrl/trunk/verif/tb
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4016d 17h /sdr_ctrl/trunk/verif/tb
56 FPGA Synth optimisation dinesha 4454d 15h /sdr_ctrl/trunk/verif/tb
53 Test bench upgradation dinesha 4458d 14h /sdr_ctrl/trunk/verif/tb
49 clean up dinesha 4461d 17h /sdr_ctrl/trunk/verif/tb
48 top-level cleanup dinesha 4461d 17h /sdr_ctrl/trunk/verif/tb
46 test bench upgrade + rtl cleanup dinesha 4463d 18h /sdr_ctrl/trunk/verif/tb
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4463d 22h /sdr_ctrl/trunk/verif/tb
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4465d 20h /sdr_ctrl/trunk/verif/tb
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4465d 22h /sdr_ctrl/trunk/verif/tb
39 Test Bench upgradation with bigger data burst size dinesha 4466d 17h /sdr_ctrl/trunk/verif/tb
38 Port Name clean up dinesha 4467d 22h /sdr_ctrl/trunk/verif/tb
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4467d 23h /sdr_ctrl/trunk/verif/tb
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4470d 15h /sdr_ctrl/trunk/verif/tb
25 tb.sv is renamed as tb_top dinesha 4471d 14h /sdr_ctrl/trunk/verif/tb
24 Clean Up dinesha 4471d 14h /sdr_ctrl/trunk/verif/tb
22 Pad sdram clock added dinesha 4472d 19h /sdr_ctrl/trunk/verif/tb
18 8 Bit SDRAM Support is added dinesha 4474d 14h /sdr_ctrl/trunk/verif/tb
14 Unnecessary device config are removed dinesha 4477d 15h /sdr_ctrl/trunk/verif/tb

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