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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_core.sv] - Rev 68

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Rev Log message Author Age Path
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3504d 15h /sdr_ctrl/trunk/verif/tb/tb_core.sv
56 FPGA Synth optimisation dinesha 3942d 14h /sdr_ctrl/trunk/verif/tb/tb_core.sv
53 Test bench upgradation dinesha 3946d 12h /sdr_ctrl/trunk/verif/tb/tb_core.sv
49 clean up dinesha 3949d 15h /sdr_ctrl/trunk/verif/tb/tb_core.sv
48 top-level cleanup dinesha 3949d 15h /sdr_ctrl/trunk/verif/tb/tb_core.sv
46 test bench upgrade + rtl cleanup dinesha 3951d 16h /sdr_ctrl/trunk/verif/tb/tb_core.sv
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 3951d 20h /sdr_ctrl/trunk/verif/tb/tb_core.sv
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 3953d 18h /sdr_ctrl/trunk/verif/tb/tb_core.sv
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 3953d 20h /sdr_ctrl/trunk/verif/tb/tb_core.sv
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 3958d 14h /sdr_ctrl/trunk/verif/tb/tb_core.sv

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