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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 30

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30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 3960d 00h /sdr_ctrl/trunk/verif/tb/tb_top.sv
25 tb.sv is renamed as tb_top dinesha 3960d 23h /sdr_ctrl/trunk/verif/tb/tb_top.sv
24 Clean Up dinesha 3960d 23h /sdr_ctrl/trunk/verif/tb/tb.sv
22 Pad sdram clock added dinesha 3962d 04h /sdr_ctrl/trunk/verif/tb/tb.sv
18 8 Bit SDRAM Support is added dinesha 3963d 23h /sdr_ctrl/trunk/verif/tb/tb.sv
14 Unnecessary device config are removed dinesha 3967d 00h /sdr_ctrl/trunk/verif/tb/tb.sv
12 Column Bits are made programmable dinesha 3967d 00h /sdr_ctrl/trunk/verif/tb/tb.sv
8 test bench files are added into SVN dinesha 3971d 01h /sdr_ctrl/trunk/verif/tb/tb.sv

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