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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 68

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Rev Log message Author Age Path
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3504d 17h /sdr_ctrl/trunk/verif/tb/tb_top.sv
56 FPGA Synth optimisation dinesha 3942d 16h /sdr_ctrl/trunk/verif/tb/tb_top.sv
53 Test bench upgradation dinesha 3946d 14h /sdr_ctrl/trunk/verif/tb/tb_top.sv
48 top-level cleanup dinesha 3949d 17h /sdr_ctrl/trunk/verif/tb/tb_top.sv
46 test bench upgrade + rtl cleanup dinesha 3951d 18h /sdr_ctrl/trunk/verif/tb/tb_top.sv
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 3951d 22h /sdr_ctrl/trunk/verif/tb/tb_top.sv
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 3953d 20h /sdr_ctrl/trunk/verif/tb/tb_top.sv
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 3953d 22h /sdr_ctrl/trunk/verif/tb/tb_top.sv
39 Test Bench upgradation with bigger data burst size dinesha 3954d 17h /sdr_ctrl/trunk/verif/tb/tb_top.sv
38 Port Name clean up dinesha 3955d 22h /sdr_ctrl/trunk/verif/tb/tb_top.sv
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 3956d 00h /sdr_ctrl/trunk/verif/tb/tb_top.sv
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 3958d 16h /sdr_ctrl/trunk/verif/tb/tb_top.sv
25 tb.sv is renamed as tb_top dinesha 3959d 14h /sdr_ctrl/trunk/verif/tb/tb_top.sv
24 Clean Up dinesha 3959d 14h /sdr_ctrl/trunk/verif/tb/tb.sv
22 Pad sdram clock added dinesha 3960d 20h /sdr_ctrl/trunk/verif/tb/tb.sv
18 8 Bit SDRAM Support is added dinesha 3962d 14h /sdr_ctrl/trunk/verif/tb/tb.sv
14 Unnecessary device config are removed dinesha 3965d 15h /sdr_ctrl/trunk/verif/tb/tb.sv
12 Column Bits are made programmable dinesha 3965d 16h /sdr_ctrl/trunk/verif/tb/tb.sv
8 test bench files are added into SVN dinesha 3969d 16h /sdr_ctrl/trunk/verif/tb/tb.sv

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