OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 73

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 355d 00h /sdr_ctrl/trunk/verif/tb/tb_top.sv
70 Warning Cleanup dinesha 3400d 01h /sdr_ctrl/trunk/verif/tb/tb_top.sv
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3400d 02h /sdr_ctrl/trunk/verif/tb/tb_top.sv
56 FPGA Synth optimisation dinesha 3838d 01h /sdr_ctrl/trunk/verif/tb/tb_top.sv
53 Test bench upgradation dinesha 3841d 23h /sdr_ctrl/trunk/verif/tb/tb_top.sv
48 top-level cleanup dinesha 3845d 02h /sdr_ctrl/trunk/verif/tb/tb_top.sv
46 test bench upgrade + rtl cleanup dinesha 3847d 03h /sdr_ctrl/trunk/verif/tb/tb_top.sv
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 3847d 08h /sdr_ctrl/trunk/verif/tb/tb_top.sv
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 3849d 06h /sdr_ctrl/trunk/verif/tb/tb_top.sv
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 3849d 07h /sdr_ctrl/trunk/verif/tb/tb_top.sv
39 Test Bench upgradation with bigger data burst size dinesha 3850d 02h /sdr_ctrl/trunk/verif/tb/tb_top.sv
38 Port Name clean up dinesha 3851d 07h /sdr_ctrl/trunk/verif/tb/tb_top.sv
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 3851d 09h /sdr_ctrl/trunk/verif/tb/tb_top.sv
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 3854d 01h /sdr_ctrl/trunk/verif/tb/tb_top.sv
25 tb.sv is renamed as tb_top dinesha 3855d 00h /sdr_ctrl/trunk/verif/tb/tb_top.sv
24 Clean Up dinesha 3855d 00h /sdr_ctrl/trunk/verif/tb/tb.sv
22 Pad sdram clock added dinesha 3856d 05h /sdr_ctrl/trunk/verif/tb/tb.sv
18 8 Bit SDRAM Support is added dinesha 3858d 00h /sdr_ctrl/trunk/verif/tb/tb.sv
14 Unnecessary device config are removed dinesha 3861d 01h /sdr_ctrl/trunk/verif/tb/tb.sv
12 Column Bits are made programmable dinesha 3861d 01h /sdr_ctrl/trunk/verif/tb/tb.sv

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.