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[/] [sdr_ctrl/] [trunk] - Rev 73

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Rev Log message Author Age Path
53 Test bench upgradation dinesha 4757d 18h /sdr_ctrl/trunk
52 Documentation update for request control and transfer control block dinesha 4757d 18h /sdr_ctrl/trunk
51 FPGA relating timing optimisation done dinesha 4757d 18h /sdr_ctrl/trunk
50 Bug fix the request length is fixe dinesha 4759d 22h /sdr_ctrl/trunk
49 clean up dinesha 4760d 21h /sdr_ctrl/trunk
48 top-level cleanup dinesha 4760d 21h /sdr_ctrl/trunk
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4760d 21h /sdr_ctrl/trunk
46 test bench upgrade + rtl cleanup dinesha 4762d 22h /sdr_ctrl/trunk
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4763d 02h /sdr_ctrl/trunk
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4765d 00h /sdr_ctrl/trunk

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