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Subversion Repositories sdr_ctrl

[/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 1134d 01h /
72 Command Clean up for model-sim mode dinesha 4127d 10h /
71 Warning cleanup dinesha 4179d 02h /
70 Warning Cleanup dinesha 4179d 02h /
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4179d 03h /
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4179d 03h /
67 time scale removed dinesha 4249d 01h /
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4497d 02h /
65 Updated Log file with CAS latency support 4,5 dinesha 4497d 10h /
64 CAS Latency support added for 4,5 dinesha 4497d 10h /
63 FPGA Bench mark results are added dinesha 4616d 09h /
62 Synthesis constraint for simplify dinesha 4616d 09h /
61 RTL file list are added into SVN dinesha 4616d 10h /
60 warning cleanup dinesha 4616d 10h /
59 Control path request and data are register now for better FPGA timing dinesha 4616d 10h /
58 Read Data is register on RD_FAST=0 case dinesha 4616d 10h /
57 Synthesis constraints are added dinesha 4617d 01h /
56 FPGA Synth optimisation dinesha 4617d 02h /
55 FPGA Synthesis timing optimisation dinesha 4617d 02h /
54 FPGA Timing Optimisation dinesha 4620d 00h /

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