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[/] [spi_master_slave/] - Rev 4

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Rev Log message Author Age Path
4 v0.97.0068 - streamlined resets and clock enables to reduce area
v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains
v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit
v0.97.0086 - removed master MISO input register: got 33MHz.
jdoin 4921d 01h /spi_master_slave/
3 - fixed fsm async glitches at state changes
- changed async clears to sync resets
- improved idle state logic for parallel interface
- added cross-clock register buffers
- exposed internal state and nets for debug
jdoin 4929d 23h /spi_master_slave/
2 v0.95.0050 - Master/Slave loopback verified at 25MHz. jdoin 4938d 05h /spi_master_slave/
1 The project and the structure was created root 4951d 23h /spi_master_slave/

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