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[/] [spi_master_slave/] - Rev 5

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Rev Log message Author Age Path
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 3574d 11h /spi_master_slave/
4 v0.97.0068 - streamlined resets and clock enables to reduce area
v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains
v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit
v0.97.0086 - removed master MISO input register: got 33MHz.
jdoin 3599d 11h /spi_master_slave/
3 - fixed fsm async glitches at state changes
- changed async clears to sync resets
- improved idle state logic for parallel interface
- added cross-clock register buffers
- exposed internal state and nets for debug
jdoin 3608d 09h /spi_master_slave/
2 v0.95.0050 - Master/Slave loopback verified at 25MHz. jdoin 3616d 15h /spi_master_slave/
1 The project and the structure was created root 3630d 09h /spi_master_slave/

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