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[/] [spi_master_slave/] [trunk/] [doc/] [src/] [spi_master_slave_Specifications.doc] - Rev 18

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Rev Log message Author Age Path
18 v2.02.0122: Fixed bug SLAVE Continuous Transfer.
The fix consists in engaging continuous transfer regardless of the user strobing write enable, and sequencing from state 1 to N as long as the master clock is present.
If the user does not write new data, the last data word is repeated.
jdoin 3396d 18h /spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
15 Updated manual text. jdoin 3401d 14h /spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
14 Updated specifications manual, deleted old documentation stuff, changed minor text errors in the code. jdoin 3402d 13h /spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
7 Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. jdoin 3423d 11h /spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 3425d 08h /spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
4 v0.97.0068 - streamlined resets and clock enables to reduce area
v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains
v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit
v0.97.0086 - removed master MISO input register: got 33MHz.
jdoin 3450d 09h /spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
2 v0.95.0050 - Master/Slave loopback verified at 25MHz. jdoin 3467d 12h /spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc

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