| Rev |
Log message |
Author |
Age |
Path |
| 14 |
Updated specifications manual, deleted old documentation stuff, changed minor text errors in the code. |
jdoin |
4797d 07h |
/spi_master_slave/trunk/rtl/ |
| 13 |
spi_slave.vhd: v2.02.0120
spi_master.vhd: v1.15.0135
Several bugs fixed. Master and Slave cores tested at all spi modes, at 50MHz SCK, including continuous transfers. |
jdoin |
4798d 02h |
/spi_master_slave/trunk/rtl/ |
| 12 |
SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks. |
jdoin |
4802d 02h |
/spi_master_slave/trunk/rtl/ |
| 11 |
v1.12.0105: Modified SCK output circuit in spi_master.vhd.
In CPHA='0', top speed is +50MHz, in CPHA='1', top speed is 25MHz. |
jdoin |
4813d 02h |
/spi_master_slave/trunk/rtl/ |
| 10 |
v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise. |
jdoin |
4814d 03h |
/spi_master_slave/trunk/rtl/ |
| 8 |
Updated Documentation |
jdoin |
4817d 15h |
/spi_master_slave/trunk/rtl/ |
| 7 |
Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. |
jdoin |
4818d 05h |
/spi_master_slave/trunk/rtl/ |
| 6 |
v1.10.0075: Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation. |
jdoin |
4820d 02h |
/spi_master_slave/trunk/rtl/ |
| 5 |
Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation. |
jdoin |
4820d 02h |
/spi_master_slave/trunk/rtl/ |
| 4 |
v0.97.0068 - streamlined resets and clock enables to reduce area
v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains
v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit
v0.97.0086 - removed master MISO input register: got 33MHz. |
jdoin |
4845d 02h |
/spi_master_slave/trunk/rtl/ |
| 3 |
- fixed fsm async glitches at state changes
- changed async clears to sync resets
- improved idle state logic for parallel interface
- added cross-clock register buffers
- exposed internal state and nets for debug |
jdoin |
4854d 00h |
/spi_master_slave/trunk/rtl/ |
| 2 |
v0.95.0050 - Master/Slave loopback verified at 25MHz. |
jdoin |
4862d 06h |
/spi_master_slave/trunk/rtl/ |
