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[/] [spi_master_slave/] [trunk/] [syn/] - Rev 11

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Rev Log message Author Age Path
11 v1.12.0105: Modified SCK output circuit in spi_master.vhd.
In CPHA='0', top speed is +50MHz, in CPHA='1', top speed is 25MHz.		 jdoin 4660d 04h /spi_master_slave/trunk/syn/
10 v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.		 jdoin 4661d 05h /spi_master_slave/trunk/syn/
9 Updated verification data. jdoin 4664d 18h /spi_master_slave/trunk/syn/
7 Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. jdoin 4665d 08h /spi_master_slave/trunk/syn/
6 v1.10.0075: Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.		 jdoin 4667d 05h /spi_master_slave/trunk/syn/
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.		 jdoin 4667d 05h /spi_master_slave/trunk/syn/

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